(a) Field of the Invention
The present invention relates to a semiconductor memory device. More particularly, the present invention relates to a flash memory device, and a manufacturing method thereof, that protects sidewalls of a floating gate and a control gate and prevents recess of an active area of a source region so as to improve the electrical characteristics and the reliability of the device.
(b) Description of the Related Art
Recently, a non-volatile memory device having a SONOS (polysilicon/oxide/nitride/oxide/semiconductor) structure has been widely noticed in that it can enhance some problems belonging to other non-volatile memory devices.
This is because the upper oxide layer, namely the top oxide, may act as a supplier of highly concentrated traps into the interface with the nitride layer as well as a potential barrier against charges that move through the gate.
Accordingly, even though the size of a memory window is maintained, the thickness of a gate insulation layer (e.g., a nitride layer) can be thinner. Therefore, a non-volatile memory device having high efficiency can be manufactured due to the lower programmable voltage for writing and erasing.
Flash memory devices that are commercially available may be divided into a stacked gate flash cell device that has a control gate and a floating gate, and a SONOS flash cell device that has a single gate and a stacked gate dielectric material (e.g., oxide/nitride/oxide (ONO) structure).
The stacked gate flash cell device is programmed and erased by using a shift of a turn-on threshold voltage of the control gate due to a local electric field that is induced by hot carriers implanted into the floating gate region by hot carrier injection.
Also the SONOS flash cell device is programmed by using hot carrier traps that are implanted from the interface between the oxide layer and the nitride layer of the ONO region or defect sites of the nitride layer as the role of the floating gate of the stacked gate flash cell device.
The programming and erasing is controlled by the shifted turn-on threshold voltage of the gate.
The major influencing issue on the working characteristics of such a flash memory device is how the hot carrier injection effect, which influences on the programming of the device, can be maximized.
Particularly, as low power consumption devices are widely developed, the device characteristics as above have become important.
Among manufacturing methods of NOR type flash memory devices, there may be a process step wherein the source region of two flash memory devices are connected. For this process, there may be a process step wherein the isolation material is removed from a shallow trench isolation (STI) structure between two flash memory devices, and a common source is formed by ion implantation into the area where the STI structure was removed.
Now, a method of manufacturing conventional flash memory devices will hereinafter be described in detail with reference to the accompanying drawings.
FIG. 1A to FIG. 1C are cross-sectional views showing principal stages of a conventional flash memory device.
The left figure of each drawing describes an active region and the right figure of each drawing describes an interface region between an active region and a device isolation region.
As shown in FIG. 1A, a device isolation layer 12 is formed on a device isolation region of semiconductor substrate 11 that is defined into an active region and a device isolation region.
Subsequently, a tunneling oxide layer 13 is formed on the active region of the semiconductor substrate 11, and then a floating gate 14, a gate insulation layer 15, and a control gate 16 are sequentially formed thereon.
The floating gate 14 and the control gate 16 are formed as described below.
Firstly, a first polysilicon layer for a floating gate is formed on the tunneling oxide layer 13 to a thickness of about 2500 Å.
Subsequently, the gate insulation layer 15 is formed on the first polysilicon layer. The gate insulation layer 15 may have an oxide layer/nitride layer/oxide layer (ONO) structure.
In order to form the gate insulation layer 15 having the ONO structure, a first oxide layer is formed by thermal oxidation of the first polysilicon layer, a silicon nitride layer may be formed on the first oxide layer by a thermal nitride-forming process, and a second oxide layer may be formed thereon by another thermal oxide-forming process.
Subsequently, a second polysilicon layer for a control gate is formed on the gate insulation layer 15 to a thickness of about 2500 Å. And then, the control gate 16 and the floating gate 14 are formed by selectively etching the second polysilicon layer, the gate insulation layer 15, and the first polysilicon layer by using a photo and etching process.
As shown in FIG. 1B, a photoresist pattern 17 is formed by coating a photoresist on the entire surface of the semiconductor substrate 11, including the floating gate 14 and the control gate 16, and patterning by an exposure and development process so as to define a source region.
Subsequently, the device isolation layer 12 is plasma-etched so that the source region is exposed using the patterned photoresist 17 as a mask. That is, in order to expose the source region, the device isolation layer 12 (and, to the extent it may be exposed, the tunneling oxide layer 13) are removed by the plasma etching process.
As shown in FIG. 1C, the photoresist 17 is removed. Although subsequent processes are not shown, a source/drain region is formed on an active region of the semiconductor substrate 11.
However, there are some drawbacks in the conventional manufacturing method of a flash memory device as described above.
That is, in that process, the floating gate and the control gate are used as an etch-stop layer. As a result, the tunneling oxide layer and the active region under the floating gate may be exposed to plasma damage. In addition, the active region A on the extended line of the floating gate is etched, so the edge may become sharp. If a voltage is applied to the active region A, an electric field may be concentrated so as to generate a leakage current, and so the reliability of the device may deteriorate.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form knowledge or other form of prior art that may be already known in this or any other country to a person of ordinary skill in the art.